transistor-models

Name: transistor-models
Author: Arcadia-1

116stars22forks

How to install transistor-models?

arcadia-1/gmoverid-skill/transistor-models

$npx -y skills add Arcadia-1/gmoverid-skill --skill transistor-models

Installs into the current project.

Summary

Complete PTM (Predictive Technology Model) MOSFET model library from mec.umn.edu/ptm, covering all nodes: bulk conventional 180/130/90/65nm, bulk HP/LP 45/32/22nm (BSIM4), and PTM-MG multi-gate FinFET 7/10/14/16/20nm (BSIM-CMG, HP + LSTP). No manual downloads required after insta

Files · 1

View on GitHub

SKILL.md

1	# Transistor Models Skill — Complete PTM Library
2
3	> Important — do not modify skill files during normal use.
4	> When using models, copy the required `.lib` files into the user's project
5	> directory (outside `.claude/`). Do not modify or delete files inside the
6	> skill's `assets/models/` directory. Only update the skill's internal files
7	> when the user explicitly asks to refresh the model library.
8
9	Source: All model files are from [PTM — Arizona State University (ptm.asu.edu)](https://ptm.asu.edu), free for academic research.
10
11	Citations:
12	- Bulk CMOS nodes: W. Zhao and Y. Cao, "New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration," IEEE Trans. Electron Devices, vol. 53, no. 11, pp. 2816–2823, Nov. 2006. doi: 10.1109/TED.2006.884077
13	- PTM-MG FinFET nodes: S. Sinha, G. Yeric, V. Chandra, B. Cline and Y. Cao, "Exploring sub-20nm FinFET design with Predictive Technology Models," DAC 2012, pp. 283–288. doi: 10.1145/2228360.2228414
14
15	---
16
17	## Directory Structure
18
19	```
20	assets/models/
21	├── bulk_cmos/ — Bulk CMOS (BSIM3v3 / BSIM4)
22	│ ├── ptm180.lib — 180nm conventional
23	│ ├── ptm130.lib — 130nm conventional
24	│ ├── ptm90.lib — 90nm conventional
25	│ ├── ptm65.lib — 65nm conventional
26	│ ├── ptm45hp.lib — 45nm HP
27	│ ├── ptm45lp.lib — 45nm LP
28	│ ├── ptm32hp.lib — 32nm HP
29	│ ├── ptm32lp.lib — 32nm LP
30	│ ├── ptm22hp.lib — 22nm HP
31	│ └── ptm22lp.lib — 22nm LP
32	└── finfet/
33	├── models — PTM-MG library entry point (.LIB ptm{n}hp / ptm{n}lstp)
34	├── param.inc — Shared parameters (fin_height/fin_width/lg/vdd, per node)
35	├── hp/ — HP nodes: {7,10,14,16,20}nfet.pm / pfet.pm
36	└── lstp/ — LSTP nodes: {7,10,14,16,20}nfet.pm / pfet.pm
37	```
38
39	---
40
41	## Model Reference
42
43	### Bulk CMOS — Conventional (BSIM3v3/BSIM4, combined NMOS+PMOS)
44
45	\| File \| Node \| VDD \| Model names \|
46	\|------\|------\|-----\|-------------\|
47	\| `bulk_cmos/ptm180.lib` \| 180nm \| 1.8V \| `NMOS` / `PMOS` \|
48	\| `bulk_cmos/ptm130.lib` \| 130nm \| 1.3V \| `nmos` / `pmos` \|
49	\| `bulk_cmos/ptm90.lib` \| 90nm \| 1.2V \| `nmos` / `pmos` \|
50	\| `bulk_cmos/ptm65.lib` \| 65nm \| 1.1V \| `nmos` / `pmos` \|
51
52	### Bulk CMOS — HP/LP (BSIM4, combined NMOS+PMOS)
53
54	\| File \| Node \| Type \| VDD \| Model names \|
55	\|------\|------\|------\|-----\|-------------\|
56	\| `bulk_cmos/ptm45hp.lib` \| 45nm \| HP \| 1.0V \| `nmos` / `pmos` \|
57	\| `bulk_cmos/ptm45lp.lib` \| 45nm \| LP \| 1.1V \| `nmos` / `pmos` \|
58	\| `bulk_cmos/ptm32hp.lib` \| 32nm \| HP \| 0.9V \| `nmos` / `pmos` \|
59	\| `bulk_cmos/ptm32lp.lib` \| 32nm \| LP \| 1.0V \| `nmos` / `pmos` \|
60	\| `bulk_cmos/ptm22hp.lib` \| 22nm \| HP \| 0.8V \| `nmos` / `pmos` \|
61	\| `bulk_cmos/ptm22lp.lib` \| 22nm \| LP \| 1.0V \| `nmos` / `pmos` \|
62
63	### FinFET — PTM-MG Multi-Gate (BSIM-CMG)
64
65	Entry file: `finfet/models` — select node and type via `.lib` section tag:
66
67	\| Tag \| Node \| Type \| VDD \|
68	\|-----\|------\|------\|-----\|
69	\| `ptm20hp` \| 20nm \| HP \| 0.9V \|
70	\| `ptm16hp` \| 16nm \| HP \| 0.85V \|
71	\| `ptm14hp` \| 14nm \| HP \| 0.8V \|
72	\| `ptm10hp` \| 10nm \| HP \| 0.75V \|
73	\| `ptm7hp` \| 7nm \| HP \| 0.7V \|
74	\| `ptm20lstp` \| 20nm \| LSTP \| 0.9V \|
75	\| `ptm16lstp` \| 16nm \| LSTP \| 0.85V \|
76	\| `ptm14lstp` \| 14nm \| LSTP \| 0.8V \|
77	\| `ptm10lstp` \| 10nm \| LSTP \| 0.75V \|
78	\| `ptm7lstp` \| 7nm \| LSTP \| 0.7V \|
79
80	FinFET model names are `nfet` / `pfet` (subckt-wrapped); use `NFIN` to set the number of fins.
81
82	---
83
84	## ngspice Usage
85
86	### Loading a Bulk CMOS File
87
88	```spice
89	* Load 45nm HP (contains both nmos and pmos models)
90	.include "models/bulk_cmos/ptm45hp.lib"
91
92	* Instantiate NMOS
93	M1 drain gate source bulk nmos W=1u L=45n
94	```
95
96	### Loading a PTM-MG FinFET
97
98	```spice
99	* Load 7nm HP FinFET
100	.lib "models/finfet/models" ptm7hp
101
102	* PTM-MG model names are nfet / pfet
103	* Use NFIN (number of fins) instead of W
104	M1 drain gate source bulk nfet NFIN=1 L=7n
105	```
106
107	---
108
109	## Model Type Quick Reference
110
111	\| Model \| ngspice LEVEL \| Applicable nodes \| Notes \|
112	\|-------\|:------------:\|-----------------\|-------\|
113	\| BSIM3v3 \| 8 \| 180nm–250nm \| Mature bulk CMOS \|
114	\| BSIM4 \| 54 \| 65nm–22nm \| Bulk HP/LP \|
115	\| BSIM-CMG \| 72 \| 7nm–20nm \| FinFET / multi-gate \|
116
117	---
118
119	## Key Parameter Quick Reference
120
121	\| Parameter \| Meaning \| Typical range \|
122	\|-----------\|---------\|--------------\|
123	\| `vth0` \| Nominal threshold voltage [V] \| NMOS: 0.3–0.5; PMOS: −0.5 to −0.3 \|
124	\| `toxe` \| Equivalent gate-oxide thickness [m] \| 1–4 nm (deep submicron) \|
125	\| `u0` \| Low-field mobility [m²/Vs] \| NMOS: 0.03–0.05; PMOS: 0.01–0.02 \|
126	\| `vsat` \| Saturation velocity [

People who liked this also viewed

6 picks

Type

transistor-models

116stars22forks

View on GitHub

How to install transistor-models?

arcadia-1/gmoverid-skill/transistor-models

$npx -y skills add Arcadia-1/gmoverid-skill --skill transistor-models

Installs into the current project.

Summary

Files · 1

View on GitHub

SKILL.md

1	# Transistor Models Skill — Complete PTM Library
2
3	> Important — do not modify skill files during normal use.
4	> When using models, copy the required `.lib` files into the user's project
5	> directory (outside `.claude/`). Do not modify or delete files inside the
6	> skill's `assets/models/` directory. Only update the skill's internal files
7	> when the user explicitly asks to refresh the model library.
8
9	Source: All model files are from [PTM — Arizona State University (ptm.asu.edu)](https://ptm.asu.edu), free for academic research.
10
11	Citations:
12	- Bulk CMOS nodes: W. Zhao and Y. Cao, "New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration," IEEE Trans. Electron Devices, vol. 53, no. 11, pp. 2816–2823, Nov. 2006. doi: 10.1109/TED.2006.884077
13	- PTM-MG FinFET nodes: S. Sinha, G. Yeric, V. Chandra, B. Cline and Y. Cao, "Exploring sub-20nm FinFET design with Predictive Technology Models," DAC 2012, pp. 283–288. doi: 10.1145/2228360.2228414
14
15	---
16
17	## Directory Structure
18
19	```
20	assets/models/
21	├── bulk_cmos/ — Bulk CMOS (BSIM3v3 / BSIM4)
22	│ ├── ptm180.lib — 180nm conventional
23	│ ├── ptm130.lib — 130nm conventional
24	│ ├── ptm90.lib — 90nm conventional
25	│ ├── ptm65.lib — 65nm conventional
26	│ ├── ptm45hp.lib — 45nm HP
27	│ ├── ptm45lp.lib — 45nm LP
28	│ ├── ptm32hp.lib — 32nm HP
29	│ ├── ptm32lp.lib — 32nm LP
30	│ ├── ptm22hp.lib — 22nm HP
31	│ └── ptm22lp.lib — 22nm LP
32	└── finfet/
33	├── models — PTM-MG library entry point (.LIB ptm{n}hp / ptm{n}lstp)
34	├── param.inc — Shared parameters (fin_height/fin_width/lg/vdd, per node)
35	├── hp/ — HP nodes: {7,10,14,16,20}nfet.pm / pfet.pm
36	└── lstp/ — LSTP nodes: {7,10,14,16,20}nfet.pm / pfet.pm
37	```
38
39	---
40
41	## Model Reference
42
43	### Bulk CMOS — Conventional (BSIM3v3/BSIM4, combined NMOS+PMOS)
44
45	\| File \| Node \| VDD \| Model names \|
46	\|------\|------\|-----\|-------------\|
47	\| `bulk_cmos/ptm180.lib` \| 180nm \| 1.8V \| `NMOS` / `PMOS` \|
48	\| `bulk_cmos/ptm130.lib` \| 130nm \| 1.3V \| `nmos` / `pmos` \|
49	\| `bulk_cmos/ptm90.lib` \| 90nm \| 1.2V \| `nmos` / `pmos` \|
50	\| `bulk_cmos/ptm65.lib` \| 65nm \| 1.1V \| `nmos` / `pmos` \|
51
52	### Bulk CMOS — HP/LP (BSIM4, combined NMOS+PMOS)
53
54	\| File \| Node \| Type \| VDD \| Model names \|
55	\|------\|------\|------\|-----\|-------------\|
56	\| `bulk_cmos/ptm45hp.lib` \| 45nm \| HP \| 1.0V \| `nmos` / `pmos` \|
57	\| `bulk_cmos/ptm45lp.lib` \| 45nm \| LP \| 1.1V \| `nmos` / `pmos` \|
58	\| `bulk_cmos/ptm32hp.lib` \| 32nm \| HP \| 0.9V \| `nmos` / `pmos` \|
59	\| `bulk_cmos/ptm32lp.lib` \| 32nm \| LP \| 1.0V \| `nmos` / `pmos` \|
60	\| `bulk_cmos/ptm22hp.lib` \| 22nm \| HP \| 0.8V \| `nmos` / `pmos` \|
61	\| `bulk_cmos/ptm22lp.lib` \| 22nm \| LP \| 1.0V \| `nmos` / `pmos` \|
62
63	### FinFET — PTM-MG Multi-Gate (BSIM-CMG)
64
65	Entry file: `finfet/models` — select node and type via `.lib` section tag:
66
67	\| Tag \| Node \| Type \| VDD \|
68	\|-----\|------\|------\|-----\|
69	\| `ptm20hp` \| 20nm \| HP \| 0.9V \|
70	\| `ptm16hp` \| 16nm \| HP \| 0.85V \|
71	\| `ptm14hp` \| 14nm \| HP \| 0.8V \|
72	\| `ptm10hp` \| 10nm \| HP \| 0.75V \|
73	\| `ptm7hp` \| 7nm \| HP \| 0.7V \|
74	\| `ptm20lstp` \| 20nm \| LSTP \| 0.9V \|
75	\| `ptm16lstp` \| 16nm \| LSTP \| 0.85V \|
76	\| `ptm14lstp` \| 14nm \| LSTP \| 0.8V \|
77	\| `ptm10lstp` \| 10nm \| LSTP \| 0.75V \|
78	\| `ptm7lstp` \| 7nm \| LSTP \| 0.7V \|
79
80	FinFET model names are `nfet` / `pfet` (subckt-wrapped); use `NFIN` to set the number of fins.
81
82	---
83
84	## ngspice Usage
85
86	### Loading a Bulk CMOS File
87
88	```spice
89	* Load 45nm HP (contains both nmos and pmos models)
90	.include "models/bulk_cmos/ptm45hp.lib"
91
92	* Instantiate NMOS
93	M1 drain gate source bulk nmos W=1u L=45n
94	```
95
96	### Loading a PTM-MG FinFET
97
98	```spice
99	* Load 7nm HP FinFET
100	.lib "models/finfet/models" ptm7hp
101
102	* PTM-MG model names are nfet / pfet
103	* Use NFIN (number of fins) instead of W
104	M1 drain gate source bulk nfet NFIN=1 L=7n
105	```
106
107	---
108
109	## Model Type Quick Reference
110
111	\| Model \| ngspice LEVEL \| Applicable nodes \| Notes \|
112	\|-------\|:------------:\|-----------------\|-------\|
113	\| BSIM3v3 \| 8 \| 180nm–250nm \| Mature bulk CMOS \|
114	\| BSIM4 \| 54 \| 65nm–22nm \| Bulk HP/LP \|
115	\| BSIM-CMG \| 72 \| 7nm–20nm \| FinFET / multi-gate \|
116
117	---
118
119	## Key Parameter Quick Reference
120
121	\| Parameter \| Meaning \| Typical range \|
122	\|-----------\|---------\|--------------\|
123	\| `vth0` \| Nominal threshold voltage [V] \| NMOS: 0.3–0.5; PMOS: −0.5 to −0.3 \|
124	\| `toxe` \| Equivalent gate-oxide thickness [m] \| 1–4 nm (deep submicron) \|
125	\| `u0` \| Low-field mobility [m²/Vs] \| NMOS: 0.03–0.05; PMOS: 0.01–0.02 \|
126	\| `vsat` \| Saturation velocity [

People who liked this also viewed

6 picks

Type