Use this skill to start or resume the VeriFlow RTL hardware design pipeline (architect to synth). Trigger this when the user asks to "run the RTL flow", "design hardware", or "start the pipeline". Pass the project directory path as the argument. Optional: append --benchmark to auto-generate a benchmark report after the pipeline completes.
How to install vf-rtl?
bjwanneng/veriflow-cc/vf-rtl
$npx -y skills add bjwanneng/veriflow-cc --skill vf-rtlInstalls into the current project.
›Prefer a prompt? Paste this to your agent
Run `npx skills use "https://github.com/bjwanneng/veriflow-cc" --skill "bjwanneng/veriflow-cc/vf-rtl"` and follow the generated skill instructions now. Read its complete output, redirecting it to a temporary file first if necessary. Resolve relative paths from the supporting-files directory it provides.
Use the skills in "https://github.com/bjwanneng/veriflow-cc" that are relevant to the current task. Run `npx skills add "https://github.com/bjwanneng/veriflow-cc"` and select the relevant skills, then follow their instructions.
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