Use when Codex needs Chinese-language Verilog or RTL design, existing-RTL analysis, verify-repair planning, controlled improvement planning, semantic comparison, debugging, troubleshooting, independent static lint, self-checking testbench scaffolds, or ASIC-quality review for a Verilog-target design, including synthesizable Verilog-2001 RTL, local or remote Vivado/xsim validation, artifact extraction, and workflow trace diagnosis.
$npx -y skills add eriemon/verilog-generator --skill verilog-generatorInstalls into the current project.
Run `npx skills use "https://github.com/eriemon/verilog-generator" --skill "eriemon/verilog-generator"` and follow the generated skill instructions now. Read its complete output, redirecting it to a temporary file first if necessary. Resolve relative paths from the supporting-files directory it provides.
Use the skills in "https://github.com/eriemon/verilog-generator" that are relevant to the current task. Run `npx skills add "https://github.com/eriemon/verilog-generator"` and select the relevant skills, then follow their instructions.