photonforge-yield-analysis

Variation-aware yield and tolerance analysis for photonic circuits with PhotonForge + Tidy3D. Build validated parametric surrogates of every subcomponent over process corners (silicon thickness, waveguide width/CD, optionally etch/sidewall/temperature) from a bounded one-time FDTD budget, then Monte-Carlo hundreds of virtual chips across wafers and lots to get functional statistics — resonance/passband shift, Q, linewidth, extinction ratio, insertion loss — as box plots, yield numbers, and lot/wafer/chip variance decompositions. Use when the user asks how fabrication variations, process corners, or wafer/lot variability affect a circuit, or asks for yield prediction, design for manufacturability (DFM), tolerance analysis, process-corner Monte Carlo over a PDK, or 'will this design survive the fab'.