code-generation-and-backends

Name: code-generation-and-backends
Author: mohitmishra786

141stars19forks

How to install code-generation-and-backends?

mohitmishra786/low-level-dev-skills/code-generation-and-backends

$npx -y skills add mohitmishra786/low-level-dev-skills --skill code-generation-and-backends

Installs into the current project.

Summary

Code generation and backends skill for LLVM targets. Use when explaining instruction selection, DAG legalization, target lowering, or adding backend support overview. Activates on queries about LLVM backend, instruction selection, target lowering, llc, TableGen, or codegen pipeli

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SKILL.md

1	# Code Generation and Backends
2
3	## Purpose
4
5	Overview LLVM (and general compiler) backend code generation: IR legalization, SelectionDAG instruction selection, register allocation, assembly emission, and what adding a new target entails — complementing IR skills and `skills/compiler-internals/llvm-passes`.
6
7	## When to Use
8
9	- Reading `llc` output for a specific target
10	- Understanding why IR type legalizer inserted extra ops
11	- Evaluating porting compiler to new architecture (high level)
12	- Debugging wrong code at asm layer (not IR)
13
14	## Workflow
15
16	### 1. Backend pipeline (LLVM)
17
18	```
19	LLVM IR per function
20	├── IR legalizer (types/ops target supports)
21	├── SelectionDAGBuilder
22	├── LegalizeTypes / LegalizeOps
23	├── Instruction selection (pattern match TableGen)
24	├── Scheduling (pre-RA)
25	├── Register allocation
26	├── Prolog/epilog insertion
27	└── AsmPrinter → .s object
28	```
29
30	### 2. llc usage
31
32	```bash
33	clang -c -emit-llvm -O2 -o foo.bc foo.c
34	llc -march=aarch64 -O2 foo.bc -o foo.s
35	llc -march=riscv64 -O2 foo.bc -o foo-rv.s
36	```
37
38	### 3. TableGen patterns (conceptual)
39
40	```tablegen
41	def ADD32rr : Pat<(add i32 GPR:$a, GPR:$b),
42	(ADD32rr GPR:$a, GPR:$b)>;
43	```
44
45	Patterns map DAG nodes to machine instructions. `.td` files define registers, calling conv, instr formats.
46
47	### 4. Calling convention lowering
48
49	ABI rules become `CC_AArch64` / `CC_X86_64` in TableGen — ties to `skills/computer-architecture/abi-and-calling-conventions`.
50
51	### 5. Target triple
52
53	```bash
54	clang --target=arm-none-eabi -c -O2 foo.c
55	llc -mtriple=thumbv7em-none-eabi foo.bc
56	```
57
58	Mismatch between triple and CPU features (`+neon`, `+crc`) causes legalizer failures or suboptimal code.
59
60	### 6. Adding a target (outline)
61
62	1. Define register classes and instr formats in TableGen
63	2. Implement lowering hooks (`TargetLowering`)
64	3. AsmPrinter and MC layer for relocations
65	4. Builtin calling convention and ELF/COFF object writer
66
67	Full port is large — reuse existing backend closest to arch.
68
69	### 7. Agent usage
70
71	```
72	/code-generation-and-backends Trace how this IR add becomes AArch64 ADD instruction
73	```
74
75	## Common Problems
76
77	\| Symptom \| Cause \| Fix \|
78	\|---------\|-------\|-----\|
79	\| `Cannot select` fatal \| Unsupported IR op on target \| Legalize or expand op \|
80	\| Wrong soft-float \| ABI mismatch \| Set `-mfloat-abi` / triple \|
81	\| Huge stack frame \| Many spills post-RA \| IR-level pressure reduction \|
82	\| llc vs clang differ \| Different targets passed \| Same `-mtriple` \|
83	\| TableGen build fail \| Syntax in .td \| `llvm-tblgen` error line \|
84
85	## Related Skills
86
87	- `skills/compiler-internals/llvm-ir-and-passes` — pre-codegen IR
88	- `skills/compiler-internals/compiler-optimizations-deep` — RA intuition
89	- `skills/compilers/cross-gcc` — embedded triples
90	- `skills/computer-architecture/abi-and-calling-conventions` — call lowering
91	- `skills/low-level-programming/assembly-arm` — read emitted asm

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code-generation-and-backends

141stars19forks

View on GitHub

How to install code-generation-and-backends?

mohitmishra786/low-level-dev-skills/code-generation-and-backends

$npx -y skills add mohitmishra786/low-level-dev-skills --skill code-generation-and-backends

Installs into the current project.

Summary

Files · 1

View on GitHub

SKILL.md

1	# Code Generation and Backends
2
3	## Purpose
4
5	Overview LLVM (and general compiler) backend code generation: IR legalization, SelectionDAG instruction selection, register allocation, assembly emission, and what adding a new target entails — complementing IR skills and `skills/compiler-internals/llvm-passes`.
6
7	## When to Use
8
9	- Reading `llc` output for a specific target
10	- Understanding why IR type legalizer inserted extra ops
11	- Evaluating porting compiler to new architecture (high level)
12	- Debugging wrong code at asm layer (not IR)
13
14	## Workflow
15
16	### 1. Backend pipeline (LLVM)
17
18	```
19	LLVM IR per function
20	├── IR legalizer (types/ops target supports)
21	├── SelectionDAGBuilder
22	├── LegalizeTypes / LegalizeOps
23	├── Instruction selection (pattern match TableGen)
24	├── Scheduling (pre-RA)
25	├── Register allocation
26	├── Prolog/epilog insertion
27	└── AsmPrinter → .s object
28	```
29
30	### 2. llc usage
31
32	```bash
33	clang -c -emit-llvm -O2 -o foo.bc foo.c
34	llc -march=aarch64 -O2 foo.bc -o foo.s
35	llc -march=riscv64 -O2 foo.bc -o foo-rv.s
36	```
37
38	### 3. TableGen patterns (conceptual)
39
40	```tablegen
41	def ADD32rr : Pat<(add i32 GPR:$a, GPR:$b),
42	(ADD32rr GPR:$a, GPR:$b)>;
43	```
44
45	Patterns map DAG nodes to machine instructions. `.td` files define registers, calling conv, instr formats.
46
47	### 4. Calling convention lowering
48
49	ABI rules become `CC_AArch64` / `CC_X86_64` in TableGen — ties to `skills/computer-architecture/abi-and-calling-conventions`.
50
51	### 5. Target triple
52
53	```bash
54	clang --target=arm-none-eabi -c -O2 foo.c
55	llc -mtriple=thumbv7em-none-eabi foo.bc
56	```
57
58	Mismatch between triple and CPU features (`+neon`, `+crc`) causes legalizer failures or suboptimal code.
59
60	### 6. Adding a target (outline)
61
62	1. Define register classes and instr formats in TableGen
63	2. Implement lowering hooks (`TargetLowering`)
64	3. AsmPrinter and MC layer for relocations
65	4. Builtin calling convention and ELF/COFF object writer
66
67	Full port is large — reuse existing backend closest to arch.
68
69	### 7. Agent usage
70
71	```
72	/code-generation-and-backends Trace how this IR add becomes AArch64 ADD instruction
73	```
74
75	## Common Problems
76
77	\| Symptom \| Cause \| Fix \|
78	\|---------\|-------\|-----\|
79	\| `Cannot select` fatal \| Unsupported IR op on target \| Legalize or expand op \|
80	\| Wrong soft-float \| ABI mismatch \| Set `-mfloat-abi` / triple \|
81	\| Huge stack frame \| Many spills post-RA \| IR-level pressure reduction \|
82	\| llc vs clang differ \| Different targets passed \| Same `-mtriple` \|
83	\| TableGen build fail \| Syntax in .td \| `llvm-tblgen` error line \|
84
85	## Related Skills
86
87	- `skills/compiler-internals/llvm-ir-and-passes` — pre-codegen IR
88	- `skills/compiler-internals/compiler-optimizations-deep` — RA intuition
89	- `skills/compilers/cross-gcc` — embedded triples
90	- `skills/computer-architecture/abi-and-calling-conventions` — call lowering
91	- `skills/low-level-programming/assembly-arm` — read emitted asm

People who liked this also viewed

6 picks

Type