cpu-pipelines-and-hazards

Name: cpu-pipelines-and-hazards
Author: mohitmishra786

61installs19forks

How to install cpu-pipelines-and-hazards?

mohitmishra786/low-level-dev-skills/cpu-pipelines-and-hazards

$npx -y skills add mohitmishra786/low-level-dev-skills --skill cpu-pipelines-and-hazards

Installs into the current project.

Summary

CPU pipeline skill for hazards, forwarding, and stalls. Use when explaining pipeline stages, data/control hazards, forwarding paths, or branch stalls in performance analysis. Activates on queries about pipeline hazard, data hazard, control hazard, forwarding, pipeline stall, or s

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SKILL.md

1	# CPU Pipelines and Hazards
2
3	## Purpose
4
5	Explain classic and modern CPU pipeline concepts: stages, data and control hazards, forwarding/bypassing, stalls, and branch handling — foundational for optimization and understanding microarchitecture counters.
6
7	## When to Use
8
9	- Interpreting pipeline stall metrics from `skills/profilers/intel-vtune-amd-uprof`
10	- Teaching why instruction order affects throughput
11	- Relating assembly scheduling to hardware behavior
12	- Debugging unexpected performance cliffs in hot loops
13
14	## Workflow
15
16	### 1. Five-stage classic pipeline (MIPS-style mental model)
17
18	```
19	IF → ID → EX → MEM → WB
20	```
21
22	Overlapped execution: instruction N in EX while N+1 in ID.
23
24	### 2. Data hazards
25
26	\| Type \| Example \| Mitigation \|
27	\|------\|---------\|------------\|
28	\| RAW (true) \| `add r1,r2,r3` then `sub r4,r1,r5` \| Forwarding from EX/MEM/WB \|
29	\| WAR / WAW \| Rare in in-order; relevant in OoO rename \| Register renaming \|
30
31	Without forwarding:
32
33	```
34	stall until writeback completes
35	```
36
37	### 3. Control hazards (branches)
38
39	```
40	Branch in ID → target unknown until EX
41	├── Predict taken/not-taken (static or dynamic)
42	├── Flush wrong-path instructions on mispredict
43	└── Penalty = pipeline depth (varies by CPU)
44	```
45
46	See `skills/computer-architecture/branch-prediction-and-speculation`.
47
48	### 4. Structural hazards
49
50	Limited functional units (single memory port) cause stalls even without dependencies.
51
52	### 5. Practical optimization hints
53
54	```c
55	/* Bad — tight dependency chain */
56	for (int i = 0; i < n; i++)
57	acc = acc + data[i]; /* each iter waits on acc */
58
59	/* Better — multiple accumulators (ILP) */
60	acc0 = acc1 = 0;
61	for (int i = 0; i < n; i += 2) {
62	acc0 += data[i];
63	acc1 += data[i+1];
64	}
65	acc = acc0 + acc1;
66	```
67
68	Pair with `skills/low-level-programming/cpu-cache-opt` — memory often dominates.
69
70	### 6. Reading uops / ports (x86)
71
72	```bash
73	perf stat -e instructions,cycles,stalls-frontend,stalls-backend ./app
74	```
75
76	VTune "Microarchitecture Exploration" maps to pipeline slots.
77
78	### 7. Agent usage
79
80	```
81	/cpu-pipelines-and-hazards Explain RAW hazard in this ARM assembly loop and how to break it
82	```
83
84	## Common Problems
85
86	\| Symptom \| Cause \| Fix \|
87	\|---------\|-------\|-----\|
88	\| High `stalls-frontend` \| I-cache misses / branch mispredict \| Align hot loop; see branch skill \|
89	\| No speedup from unroll \| Memory bound \| Profile loads; prefetch \|
90	\| Wrong cycle model \| Ignored OoO execution \| Use perf hardware counters \|
91	\| "NOP fixes it" \| Timing-sensitive MMIO \| Never tune device delays by NOP \|
92
93	## Related Skills
94
95	- `skills/computer-architecture/branch-prediction-and-speculation` — mispredict cost
96	- `skills/computer-architecture/memory-hierarchy-and-caches` — load latency
97	- `skills/low-level-programming/cpu-cache-opt` — cache-line effects
98	- `skills/profilers/intel-vtune-amd-uprof` — pipeline analysis
99	- `skills/low-level-programming/assembly-arm` — instruction scheduling

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cpu-pipelines-and-hazards

61installs19forks

View on GitHub

How to install cpu-pipelines-and-hazards?

mohitmishra786/low-level-dev-skills/cpu-pipelines-and-hazards

$npx -y skills add mohitmishra786/low-level-dev-skills --skill cpu-pipelines-and-hazards

Installs into the current project.

Summary

Files · 1

View on GitHub

SKILL.md

1	# CPU Pipelines and Hazards
2
3	## Purpose
4
5	Explain classic and modern CPU pipeline concepts: stages, data and control hazards, forwarding/bypassing, stalls, and branch handling — foundational for optimization and understanding microarchitecture counters.
6
7	## When to Use
8
9	- Interpreting pipeline stall metrics from `skills/profilers/intel-vtune-amd-uprof`
10	- Teaching why instruction order affects throughput
11	- Relating assembly scheduling to hardware behavior
12	- Debugging unexpected performance cliffs in hot loops
13
14	## Workflow
15
16	### 1. Five-stage classic pipeline (MIPS-style mental model)
17
18	```
19	IF → ID → EX → MEM → WB
20	```
21
22	Overlapped execution: instruction N in EX while N+1 in ID.
23
24	### 2. Data hazards
25
26	\| Type \| Example \| Mitigation \|
27	\|------\|---------\|------------\|
28	\| RAW (true) \| `add r1,r2,r3` then `sub r4,r1,r5` \| Forwarding from EX/MEM/WB \|
29	\| WAR / WAW \| Rare in in-order; relevant in OoO rename \| Register renaming \|
30
31	Without forwarding:
32
33	```
34	stall until writeback completes
35	```
36
37	### 3. Control hazards (branches)
38
39	```
40	Branch in ID → target unknown until EX
41	├── Predict taken/not-taken (static or dynamic)
42	├── Flush wrong-path instructions on mispredict
43	└── Penalty = pipeline depth (varies by CPU)
44	```
45
46	See `skills/computer-architecture/branch-prediction-and-speculation`.
47
48	### 4. Structural hazards
49
50	Limited functional units (single memory port) cause stalls even without dependencies.
51
52	### 5. Practical optimization hints
53
54	```c
55	/* Bad — tight dependency chain */
56	for (int i = 0; i < n; i++)
57	acc = acc + data[i]; /* each iter waits on acc */
58
59	/* Better — multiple accumulators (ILP) */
60	acc0 = acc1 = 0;
61	for (int i = 0; i < n; i += 2) {
62	acc0 += data[i];
63	acc1 += data[i+1];
64	}
65	acc = acc0 + acc1;
66	```
67
68	Pair with `skills/low-level-programming/cpu-cache-opt` — memory often dominates.
69
70	### 6. Reading uops / ports (x86)
71
72	```bash
73	perf stat -e instructions,cycles,stalls-frontend,stalls-backend ./app
74	```
75
76	VTune "Microarchitecture Exploration" maps to pipeline slots.
77
78	### 7. Agent usage
79
80	```
81	/cpu-pipelines-and-hazards Explain RAW hazard in this ARM assembly loop and how to break it
82	```
83
84	## Common Problems
85
86	\| Symptom \| Cause \| Fix \|
87	\|---------\|-------\|-----\|
88	\| High `stalls-frontend` \| I-cache misses / branch mispredict \| Align hot loop; see branch skill \|
89	\| No speedup from unroll \| Memory bound \| Profile loads; prefetch \|
90	\| Wrong cycle model \| Ignored OoO execution \| Use perf hardware counters \|
91	\| "NOP fixes it" \| Timing-sensitive MMIO \| Never tune device delays by NOP \|
92
93	## Related Skills
94
95	- `skills/computer-architecture/branch-prediction-and-speculation` — mispredict cost
96	- `skills/computer-architecture/memory-hierarchy-and-caches` — load latency
97	- `skills/low-level-programming/cpu-cache-opt` — cache-line effects
98	- `skills/profilers/intel-vtune-amd-uprof` — pipeline analysis
99	- `skills/low-level-programming/assembly-arm` — instruction scheduling

People who liked this also viewed

6 picks

Type