dma-baremetal

Name: dma-baremetal
Author: mohitmishra786

141stars19forks

How to install dma-baremetal?

mohitmishra786/low-level-dev-skills/dma-baremetal

$npx -y skills add mohitmishra786/low-level-dev-skills --skill dma-baremetal

Installs into the current project.

Summary

Bare-metal DMA skill for memory-peripheral transfers. Use when configuring DMA channels, circular mode, double buffering, or DMA IRQ completion. Activates on queries about DMA bare-metal, circular buffer, memory-to-peripheral, or DMA stream configuration.

Files · 1

View on GitHub

SKILL.md

1	# DMA (Bare-Metal)
2
3	## Purpose
4
5	Configure DMA controllers for memory-to-peripheral and peripheral-to-memory transfers: channel/stream setup, burst sizes, circular mode, half-transfer interrupts, and cache coherency on Cortex-M7.
6
7	## When to Use
8
9	- Offloading UART/SPI/ADC bulk transfers from CPU
10	- Audio/streaming double buffers
11	- Debugging DMA not triggering or corrupt data
12
13	## Workflow
14
15	### 1. STM32 DMA2 stream (periph→mem)
16
17	```c
18	/* UART2 RX DMA — Stream5, Channel 4 (verify RM matrix) */
19	RCC->AHB1ENR \|= RCC_AHB1ENR_DMA1EN;
20
21	DMA1_Stream5->PAR = (uint32_t)&USART2->DR;
22	DMA1_Stream5->M0AR = (uint32_t)rx_buf;
23	DMA1_Stream5->NDTR = sizeof(rx_buf);
24	DMA1_Stream5->CR = DMA_SxCR_MINC /* mem increment */
25	\| DMA_SxCR_TCIE /* transfer complete IRQ */
26	\| DMA_SxCR_CHSEL_2 /* channel 4 */
27	\| DMA_SxCR_EN;
28
29	USART2->CR3 \|= USART_CR3_DMAR;
30	```
31
32	### 2. Circular / double buffer
33
34	```c
35	DMA1_Stream5->CR \|= DMA_SxCR_CIRC; /* auto-reload NDTR */
36	/* HTIF = first half, TCIF = second half — process in IRQ */
37	```
38
39	### 3. Cortex-M7 cache (H7)
40
41	DMA buffer in non-cacheable region or clean/invalidate D-Cache:
42
43	```c
44	SCB_CleanDCache_by_Addr((void*)tx_buf, len);
45	/* after DMA TX */
46	SCB_InvalidateDCache_by_Addr((void*)rx_buf, len);
47	```
48
49	### 4. Agent usage
50
51	```
52	/dma-baremetal Configure UART RX DMA circular buffer on STM32F4
53	```
54
55	## Common Problems
56
57	\| Symptom \| Cause \| Fix \|
58	\|---------\|-------\|-----\|
59	\| DMA no start \| Stream/channel mismatch \| RM DMA request mapping table \|
60	\| Corrupt RX \| Cache coherency (M7) \| Invalidate after RX complete \|
61	\| NDTR stuck \| Peripheral DMA enable missing \| USART_CR3 DMAR/DMAT \|
62	\| IRQ flood \| Clear flags in ISR \| `DMA_LISR`/`HIFCR` \|
63
64	## Related Skills
65
66	- `skills/baremetal/uart-serial-baremetal` — USART DMA enable
67	- `skills/baremetal/adc-dac-baremetal` — ADC DMA mode
68	- `skills/low-level-programming/cpu-cache-opt` — cache line concepts

People who liked this also viewed

6 picks

Type

dma-baremetal

141stars19forks

View on GitHub

How to install dma-baremetal?

mohitmishra786/low-level-dev-skills/dma-baremetal

$npx -y skills add mohitmishra786/low-level-dev-skills --skill dma-baremetal

Installs into the current project.

Summary

Files · 1

View on GitHub

SKILL.md

1	# DMA (Bare-Metal)
2
3	## Purpose
4
5	Configure DMA controllers for memory-to-peripheral and peripheral-to-memory transfers: channel/stream setup, burst sizes, circular mode, half-transfer interrupts, and cache coherency on Cortex-M7.
6
7	## When to Use
8
9	- Offloading UART/SPI/ADC bulk transfers from CPU
10	- Audio/streaming double buffers
11	- Debugging DMA not triggering or corrupt data
12
13	## Workflow
14
15	### 1. STM32 DMA2 stream (periph→mem)
16
17	```c
18	/* UART2 RX DMA — Stream5, Channel 4 (verify RM matrix) */
19	RCC->AHB1ENR \|= RCC_AHB1ENR_DMA1EN;
20
21	DMA1_Stream5->PAR = (uint32_t)&USART2->DR;
22	DMA1_Stream5->M0AR = (uint32_t)rx_buf;
23	DMA1_Stream5->NDTR = sizeof(rx_buf);
24	DMA1_Stream5->CR = DMA_SxCR_MINC /* mem increment */
25	\| DMA_SxCR_TCIE /* transfer complete IRQ */
26	\| DMA_SxCR_CHSEL_2 /* channel 4 */
27	\| DMA_SxCR_EN;
28
29	USART2->CR3 \|= USART_CR3_DMAR;
30	```
31
32	### 2. Circular / double buffer
33
34	```c
35	DMA1_Stream5->CR \|= DMA_SxCR_CIRC; /* auto-reload NDTR */
36	/* HTIF = first half, TCIF = second half — process in IRQ */
37	```
38
39	### 3. Cortex-M7 cache (H7)
40
41	DMA buffer in non-cacheable region or clean/invalidate D-Cache:
42
43	```c
44	SCB_CleanDCache_by_Addr((void*)tx_buf, len);
45	/* after DMA TX */
46	SCB_InvalidateDCache_by_Addr((void*)rx_buf, len);
47	```
48
49	### 4. Agent usage
50
51	```
52	/dma-baremetal Configure UART RX DMA circular buffer on STM32F4
53	```
54
55	## Common Problems
56
57	\| Symptom \| Cause \| Fix \|
58	\|---------\|-------\|-----\|
59	\| DMA no start \| Stream/channel mismatch \| RM DMA request mapping table \|
60	\| Corrupt RX \| Cache coherency (M7) \| Invalidate after RX complete \|
61	\| NDTR stuck \| Peripheral DMA enable missing \| USART_CR3 DMAR/DMAT \|
62	\| IRQ flood \| Clear flags in ISR \| `DMA_LISR`/`HIFCR` \|
63
64	## Related Skills
65
66	- `skills/baremetal/uart-serial-baremetal` — USART DMA enable
67	- `skills/baremetal/adc-dac-baremetal` — ADC DMA mode
68	- `skills/low-level-programming/cpu-cache-opt` — cache line concepts

People who liked this also viewed

6 picks

Type