gpio-baremetal

Name: gpio-baremetal
Author: mohitmishra786

62installs19forks

How to install gpio-baremetal?

mohitmishra786/low-level-dev-skills/gpio-baremetal

$npx -y skills add mohitmishra786/low-level-dev-skills --skill gpio-baremetal

Installs into the current project.

Summary

Bare-metal GPIO skill for pin configuration and interrupts. Use when configuring GPIO modes, alternate functions, pull resistors, or EXTI interrupts on STM32/nRF/ESP32-class MCUs. Activates on queries about GPIO MODER, alternate function, pin interrupt, or LED/button bare-metal s

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SKILL.md

1	# GPIO (Bare-Metal)
2
3	## Purpose
4
5	Configure and use GPIO without HAL: input/output modes, alternate function mapping, pull-up/down, speed/slew, and pin-change interrupts for LEDs, buttons, and peripheral pin mux.
6
7	## When to Use
8
9	- Blink LED or read button before bringing up UART/SPI
10	- Mux pins to USART/SPI alternate functions
11	- EXTI line interrupts on pin edges
12	- Porting GPIO code between vendors
13
14	## Workflow
15
16	### 1. STM32 GPIO pattern
17
18	```c
19	/* Enable GPIOA clock */
20	RCC->AHB1ENR \|= RCC_AHB1ENR_GPIOAEN;
21
22	/* PA5 output — MODER[11:10] = 01 */
23	GPIOA->MODER &= ~(3U << (5 * 2));
24	GPIOA->MODER \|= (1U << (5 * 2));
25
26	/* Toggle via BSRR — atomic set/reset */
27	GPIOA->BSRR = (1U << 5); /* set */
28	GPIOA->BSRR = (1U << (5+16)); /* reset */
29	```
30
31	Alternate function (e.g., USART2 TX on PA2):
32
33	```c
34	GPIOA->MODER &= ~(3U << (2*2));
35	GPIOA->MODER \|= (2U << (22)); / AF mode */
36	GPIOA->AFR[0] &= ~(0xFU << (2*4));
37	GPIOA->AFR[0] \|= (7U << (24)); / AF7 = USART2 */
38	```
39
40	### 2. Input with pull-up
41
42	```c
43	/* PC13 input, pull-up */
44	GPIOC->MODER &= ~(3U << (132)); / input mode 00 */
45	GPIOC->PUPDR &= ~(3U << (13*2));
46	GPIOC->PUPDR \|= (1U << (132)); / pull-up */
47
48	int pressed = !(GPIOC->IDR & (1U << 13)); /* active low */
49	```
50
51	### 3. EXTI interrupt (STM32)
52
53	```c
54	/* SYSCFG: map EXTI13 to PC13 */
55	SYSCFG->EXTICR[3] = (SYSCFG->EXTICR[3] & ~0xFU) \| 0x2; /* port C */
56	EXTI->IMR \|= (1U << 13);
57	EXTI->FTSR \|= (1U << 13); /* falling edge */
58	NVIC_EnableIRQ(EXTI15_10_IRQn);
59	```
60
61	ISR: check `EXTI->PR`, clear with write-1.
62
63	### 4. nRF52 / ESP32 notes
64
65	\| Platform \| Pattern \|
66	\|----------\|---------\|
67	\| nRF52 \| `NRF_P0->PIN_CNF[n]` — direction, pull, drive \|
68	\| ESP32 \| `GPIO.out_w1ts`, `GPIO.enable`; IO_MUX for function \|
69
70	Always enable peripheral clock / power domain before pin config.
71
72	### 5. Agent usage
73
74	```
75	/gpio-baremetal Configure PA2 as USART2 TX alternate function on STM32F4
76	```
77
78	## Common Problems
79
80	\| Symptom \| Cause \| Fix \|
81	\|---------\|-------\|-----\|
82	\| Pin stuck \| Wrong MODER / not AF \| Re-read RM pin table \|
83	\| EXTI storm \| No debounce / floating input \| Enable pull; debounce in software \|
84	\| AF mismatch \| Wrong AFR nibble \| Pin-specific AF table in RM \|
85	\| No toggle visible \| Wrong port bit / LED active low \| Check schematic \|
86
87	## Related Skills
88
89	- `skills/baremetal/mmio-and-bit-manipulation` — BSRR/MODER masks
90	- `skills/baremetal/peripherals-from-datasheet` — RM pinout tables
91	- `skills/baremetal/uart-serial-baremetal` — AF mux for serial

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gpio-baremetal

62installs19forks

View on GitHub

How to install gpio-baremetal?

mohitmishra786/low-level-dev-skills/gpio-baremetal

$npx -y skills add mohitmishra786/low-level-dev-skills --skill gpio-baremetal

Installs into the current project.

Summary

Files · 1

View on GitHub

SKILL.md

1	# GPIO (Bare-Metal)
2
3	## Purpose
4
5	Configure and use GPIO without HAL: input/output modes, alternate function mapping, pull-up/down, speed/slew, and pin-change interrupts for LEDs, buttons, and peripheral pin mux.
6
7	## When to Use
8
9	- Blink LED or read button before bringing up UART/SPI
10	- Mux pins to USART/SPI alternate functions
11	- EXTI line interrupts on pin edges
12	- Porting GPIO code between vendors
13
14	## Workflow
15
16	### 1. STM32 GPIO pattern
17
18	```c
19	/* Enable GPIOA clock */
20	RCC->AHB1ENR \|= RCC_AHB1ENR_GPIOAEN;
21
22	/* PA5 output — MODER[11:10] = 01 */
23	GPIOA->MODER &= ~(3U << (5 * 2));
24	GPIOA->MODER \|= (1U << (5 * 2));
25
26	/* Toggle via BSRR — atomic set/reset */
27	GPIOA->BSRR = (1U << 5); /* set */
28	GPIOA->BSRR = (1U << (5+16)); /* reset */
29	```
30
31	Alternate function (e.g., USART2 TX on PA2):
32
33	```c
34	GPIOA->MODER &= ~(3U << (2*2));
35	GPIOA->MODER \|= (2U << (22)); / AF mode */
36	GPIOA->AFR[0] &= ~(0xFU << (2*4));
37	GPIOA->AFR[0] \|= (7U << (24)); / AF7 = USART2 */
38	```
39
40	### 2. Input with pull-up
41
42	```c
43	/* PC13 input, pull-up */
44	GPIOC->MODER &= ~(3U << (132)); / input mode 00 */
45	GPIOC->PUPDR &= ~(3U << (13*2));
46	GPIOC->PUPDR \|= (1U << (132)); / pull-up */
47
48	int pressed = !(GPIOC->IDR & (1U << 13)); /* active low */
49	```
50
51	### 3. EXTI interrupt (STM32)
52
53	```c
54	/* SYSCFG: map EXTI13 to PC13 */
55	SYSCFG->EXTICR[3] = (SYSCFG->EXTICR[3] & ~0xFU) \| 0x2; /* port C */
56	EXTI->IMR \|= (1U << 13);
57	EXTI->FTSR \|= (1U << 13); /* falling edge */
58	NVIC_EnableIRQ(EXTI15_10_IRQn);
59	```
60
61	ISR: check `EXTI->PR`, clear with write-1.
62
63	### 4. nRF52 / ESP32 notes
64
65	\| Platform \| Pattern \|
66	\|----------\|---------\|
67	\| nRF52 \| `NRF_P0->PIN_CNF[n]` — direction, pull, drive \|
68	\| ESP32 \| `GPIO.out_w1ts`, `GPIO.enable`; IO_MUX for function \|
69
70	Always enable peripheral clock / power domain before pin config.
71
72	### 5. Agent usage
73
74	```
75	/gpio-baremetal Configure PA2 as USART2 TX alternate function on STM32F4
76	```
77
78	## Common Problems
79
80	\| Symptom \| Cause \| Fix \|
81	\|---------\|-------\|-----\|
82	\| Pin stuck \| Wrong MODER / not AF \| Re-read RM pin table \|
83	\| EXTI storm \| No debounce / floating input \| Enable pull; debounce in software \|
84	\| AF mismatch \| Wrong AFR nibble \| Pin-specific AF table in RM \|
85	\| No toggle visible \| Wrong port bit / LED active low \| Check schematic \|
86
87	## Related Skills
88
89	- `skills/baremetal/mmio-and-bit-manipulation` — BSRR/MODER masks
90	- `skills/baremetal/peripherals-from-datasheet` — RM pinout tables
91	- `skills/baremetal/uart-serial-baremetal` — AF mux for serial

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6 picks

Type