mmio-and-bit-manipulation

Name: mmio-and-bit-manipulation
Author: mohitmishra786

62installs19forks

How to install mmio-and-bit-manipulation?

mohitmishra786/low-level-dev-skills/mmio-and-bit-manipulation

$npx -y skills add mohitmishra786/low-level-dev-skills --skill mmio-and-bit-manipulation

Installs into the current project.

Summary

MMIO and register access skill for bare-metal firmware. Use when accessing memory-mapped peripherals with volatile, bit masks, RMW patterns, or endianness concerns. Activates on queries about MMIO, volatile register, bit manipulation, read-modify-write, or register alignment.

Files · 1

View on GitHub

SKILL.md

1	# MMIO and Bit Manipulation
2
3	## Purpose
4
5	Guide agents through safe memory-mapped I/O: `volatile` semantics, read-modify-write patterns, bitfield pitfalls, alignment and endianness, and portable register access macros for bare-metal drivers.
6
7	## When to Use
8
9	- Writing peripheral register drivers without HAL
10	- Fixing intermittent register corruption or stale reads
11	- Replacing C bitfields with explicit masks
12	- Porting drivers between little-endian MCUs
13	- Auditing ISR vs main-line register access
14
15	## Workflow
16
17	### 1. MMIO fundamentals
18
19	Peripheral registers live at fixed addresses in the CPU memory map. The compiler must not cache reads/writes.
20
21	```c
22	#include <stdint.h>
23
24	#define PERIPH_BASE 0x40000000U
25	#define GPIOA_MODER ((volatile uint32_t )(PERIPH_BASE + 0x20000U))
26	```
27
28	\| Qualifier \| Effect \|
29	\|-----------\|--------\|
30	\| `volatile` \| Forces load/store each access — required for hardware \|
31	\| `const volatile` \| Read-only hardware (rare) \|
32	\| Plain `uint32_t ` \| Wrong* — compiler may optimize away \|
33
34	### 2. Read-modify-write macros
35
36	```c
37	#define REG32(addr) ((volatile uint32_t )(addr))
38	#define REG_SET(addr, mask) (REG32(addr) \|= (mask))
39	#define REG_CLR(addr, mask) (REG32(addr) &= ~(mask))
40	#define REG_TOGGLE(addr, mask) (REG32(addr) ^= (mask))
41	#define REG_WRITE(addr, val) (REG32(addr) = (val))
42	#define REG_READ(addr) (REG32(addr))
43	```
44
45	Good — atomic intent for single-bit updates when register supports it:
46
47	```c
48	#define GPIOA_BSRR REG32(0x40020018U)
49	GPIOA_BSRR = (1U << 5); /* set PA5 */
50	GPIOA_BSRR = (1U << (5+16)); /* reset PA5 — STM32 BSRR pattern */
51	```
52
53	Bad — non-atomic RMW on interrupt-shared registers:
54
55	```c
56	uint32_t v = REG_READ(GPIOA_MODER);
57	v \|= (1U << 10);
58	REG_WRITE(GPIOA_MODER, v); /* ISR may interleave — lost update */
59	```
60
61	Fix: disable IRQ briefly, use hardware set/clear registers, or LL atomic bitband if available.
62
63	### 3. Bitfield pitfalls
64
65	```c
66	/* Bad — layout is implementation-defined, not portable */
67	typedef struct {
68	uint32_t mode : 2;
69	uint32_t type : 1;
70	uint32_t speed : 2;
71	} gpio_moder_bits_t;
72	```
73
74	Prefer explicit masks:
75
76	```c
77	#define GPIO_MODER_MODE0_SHIFT 0
78	#define GPIO_MODER_MODE0_MASK (3U << GPIO_MODER_MODE0_SHIFT)
79	#define GPIO_MODER_MODE0_VAL(n) ((n) << GPIO_MODER_MODE0_SHIFT)
80
81	REG32(GPIOA_MODER) = (REG32(GPIOA_MODER) & ~GPIO_MODER_MODE0_MASK)
82	\| GPIO_MODER_MODE0_VAL(1); /* output */
83	```
84
85	### 4. Endianness and alignment
86
87	- Cortex-M and most MCUs: little-endian — `uint32_t` MMIO at word-aligned addresses
88	- Unaligned `uint32_t` access may fault on ARMv7-M+
89	- 8-bit registers: use `volatile uint8_t` with correct byte lane address
90
91	```c
92	#define REG8(addr) ((volatile uint8_t )(addr))
93	```
94
95	### 5. Memory barriers (when needed)
96
97	```c
98	/* After configuring peripheral before first use */
99	__DSB();
100	__ISB();
101
102	/* After DMA setup, before enabling channel */
103	__DMB();
104	```
105
106	Use CMSIS barriers (`core_cm4.h`) on Cortex-M.
107
108	### 6. Agent usage examples
109
110	```
111	/mmio-and-bit-manipulation Safe pattern to set bit 3 without affecting other bits in ISR context
112	/mmio-and-bit-manipulation Why must peripheral pointers be volatile?
113	```
114
115	## Common Problems
116
117	\| Symptom \| Cause \| Fix \|
118	\|---------\|-------\|-----\|
119	\| Register write ignored \| Wrong address/clock gated \| Enable peripheral clock first \|
120	\| Random bit flips \| RMW race with ISR \| BSRR-style atomic regs or critical section \|
121	\| HardFault on access \| Unaligned or protected bus \| Match access width to datasheet \|
122	\| Optimized-away read \| Missing `volatile` \| Use `volatile uint32_t` \|
123	\| Bitfield wrong value \| Compiler packs unexpectedly \| Use shift/mask macros \|
124
125	## Related Skills
126
127	- `skills/baremetal/peripherals-from-datasheet` — extracting register maps
128	- `skills/baremetal/gpio-baremetal` — GPIO register patterns
129	- `skills/low-level-programming/assembly-arm` — inline asm barriers
130	- `skills/embedded/linker-scripts` — peripheral memory map regions

People who liked this also viewed

6 picks

Type

mmio-and-bit-manipulation

62installs19forks

View on GitHub

How to install mmio-and-bit-manipulation?

mohitmishra786/low-level-dev-skills/mmio-and-bit-manipulation

$npx -y skills add mohitmishra786/low-level-dev-skills --skill mmio-and-bit-manipulation

Installs into the current project.

Summary

Files · 1

View on GitHub

SKILL.md

1	# MMIO and Bit Manipulation
2
3	## Purpose
4
5	Guide agents through safe memory-mapped I/O: `volatile` semantics, read-modify-write patterns, bitfield pitfalls, alignment and endianness, and portable register access macros for bare-metal drivers.
6
7	## When to Use
8
9	- Writing peripheral register drivers without HAL
10	- Fixing intermittent register corruption or stale reads
11	- Replacing C bitfields with explicit masks
12	- Porting drivers between little-endian MCUs
13	- Auditing ISR vs main-line register access
14
15	## Workflow
16
17	### 1. MMIO fundamentals
18
19	Peripheral registers live at fixed addresses in the CPU memory map. The compiler must not cache reads/writes.
20
21	```c
22	#include <stdint.h>
23
24	#define PERIPH_BASE 0x40000000U
25	#define GPIOA_MODER ((volatile uint32_t )(PERIPH_BASE + 0x20000U))
26	```
27
28	\| Qualifier \| Effect \|
29	\|-----------\|--------\|
30	\| `volatile` \| Forces load/store each access — required for hardware \|
31	\| `const volatile` \| Read-only hardware (rare) \|
32	\| Plain `uint32_t ` \| Wrong* — compiler may optimize away \|
33
34	### 2. Read-modify-write macros
35
36	```c
37	#define REG32(addr) ((volatile uint32_t )(addr))
38	#define REG_SET(addr, mask) (REG32(addr) \|= (mask))
39	#define REG_CLR(addr, mask) (REG32(addr) &= ~(mask))
40	#define REG_TOGGLE(addr, mask) (REG32(addr) ^= (mask))
41	#define REG_WRITE(addr, val) (REG32(addr) = (val))
42	#define REG_READ(addr) (REG32(addr))
43	```
44
45	Good — atomic intent for single-bit updates when register supports it:
46
47	```c
48	#define GPIOA_BSRR REG32(0x40020018U)
49	GPIOA_BSRR = (1U << 5); /* set PA5 */
50	GPIOA_BSRR = (1U << (5+16)); /* reset PA5 — STM32 BSRR pattern */
51	```
52
53	Bad — non-atomic RMW on interrupt-shared registers:
54
55	```c
56	uint32_t v = REG_READ(GPIOA_MODER);
57	v \|= (1U << 10);
58	REG_WRITE(GPIOA_MODER, v); /* ISR may interleave — lost update */
59	```
60
61	Fix: disable IRQ briefly, use hardware set/clear registers, or LL atomic bitband if available.
62
63	### 3. Bitfield pitfalls
64
65	```c
66	/* Bad — layout is implementation-defined, not portable */
67	typedef struct {
68	uint32_t mode : 2;
69	uint32_t type : 1;
70	uint32_t speed : 2;
71	} gpio_moder_bits_t;
72	```
73
74	Prefer explicit masks:
75
76	```c
77	#define GPIO_MODER_MODE0_SHIFT 0
78	#define GPIO_MODER_MODE0_MASK (3U << GPIO_MODER_MODE0_SHIFT)
79	#define GPIO_MODER_MODE0_VAL(n) ((n) << GPIO_MODER_MODE0_SHIFT)
80
81	REG32(GPIOA_MODER) = (REG32(GPIOA_MODER) & ~GPIO_MODER_MODE0_MASK)
82	\| GPIO_MODER_MODE0_VAL(1); /* output */
83	```
84
85	### 4. Endianness and alignment
86
87	- Cortex-M and most MCUs: little-endian — `uint32_t` MMIO at word-aligned addresses
88	- Unaligned `uint32_t` access may fault on ARMv7-M+
89	- 8-bit registers: use `volatile uint8_t` with correct byte lane address
90
91	```c
92	#define REG8(addr) ((volatile uint8_t )(addr))
93	```
94
95	### 5. Memory barriers (when needed)
96
97	```c
98	/* After configuring peripheral before first use */
99	__DSB();
100	__ISB();
101
102	/* After DMA setup, before enabling channel */
103	__DMB();
104	```
105
106	Use CMSIS barriers (`core_cm4.h`) on Cortex-M.
107
108	### 6. Agent usage examples
109
110	```
111	/mmio-and-bit-manipulation Safe pattern to set bit 3 without affecting other bits in ISR context
112	/mmio-and-bit-manipulation Why must peripheral pointers be volatile?
113	```
114
115	## Common Problems
116
117	\| Symptom \| Cause \| Fix \|
118	\|---------\|-------\|-----\|
119	\| Register write ignored \| Wrong address/clock gated \| Enable peripheral clock first \|
120	\| Random bit flips \| RMW race with ISR \| BSRR-style atomic regs or critical section \|
121	\| HardFault on access \| Unaligned or protected bus \| Match access width to datasheet \|
122	\| Optimized-away read \| Missing `volatile` \| Use `volatile uint32_t` \|
123	\| Bitfield wrong value \| Compiler packs unexpectedly \| Use shift/mask macros \|
124
125	## Related Skills
126
127	- `skills/baremetal/peripherals-from-datasheet` — extracting register maps
128	- `skills/baremetal/gpio-baremetal` — GPIO register patterns
129	- `skills/low-level-programming/assembly-arm` — inline asm barriers
130	- `skills/embedded/linker-scripts` — peripheral memory map regions

People who liked this also viewed

6 picks

Type