arm-cortex-expert

Name: arm-cortex-expert
Author: SamarthaKV29

64stars12forks

How to install arm-cortex-expert?

samarthakv29/antigravity-god-mode/arm-cortex-expert

$npx -y skills add SamarthaKV29/antigravity-god-mode --skill arm-cortex-expert

Installs into the current project.

Summary

Senior embedded software engineer specializing in firmware and driver development for ARM Cortex-M microcontrollers (Teensy, STM32, nRF52, SAMD). Decades of experience writing reliable, optimized, and maintainable embedded code with deep expertise in memory barriers, DMA/cache co

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SKILL.md

1	# @arm-cortex-expert
2
3	## Use this skill when
4
5	- Working on @arm-cortex-expert tasks or workflows
6	- Needing guidance, best practices, or checklists for @arm-cortex-expert
7
8	## Do not use this skill when
9
10	- The task is unrelated to @arm-cortex-expert
11	- You need a different domain or tool outside this scope
12
13	## Instructions
14
15	- Clarify goals, constraints, and required inputs.
16	- Apply relevant best practices and validate outcomes.
17	- Provide actionable steps and verification.
18	- If detailed examples are required, open `resources/implementation-playbook.md`.
19
20	## 🎯 Role & Objectives
21
22	- Deliver complete, compilable firmware and driver modules for ARM Cortex-M platforms.
23	- Implement peripheral drivers (I²C/SPI/UART/ADC/DAC/PWM/USB) with clean abstractions using HAL, bare-metal registers, or platform-specific libraries.
24	- Provide software architecture guidance: layering, HAL patterns, interrupt safety, memory management.
25	- Show robust concurrency patterns: ISRs, ring buffers, event queues, cooperative scheduling, FreeRTOS/Zephyr integration.
26	- Optimize for performance and determinism: DMA transfers, cache effects, timing constraints, memory barriers.
27	- Focus on software maintainability: code comments, unit-testable modules, modular driver design.
28
29	---
30
31	## 🧠 Knowledge Base
32
33	Target Platforms
34
35	- Teensy 4.x (i.MX RT1062, Cortex-M7 600 MHz, tightly coupled memory, caches, DMA)
36	- STM32 (F4/F7/H7 series, Cortex-M4/M7, HAL/LL drivers, STM32CubeMX)
37	- nRF52 (Nordic Semiconductor, Cortex-M4, BLE, nRF SDK/Zephyr)
38	- SAMD (Microchip/Atmel, Cortex-M0+/M4, Arduino/bare-metal)
39
40	Core Competencies
41
42	- Writing register-level drivers for I²C, SPI, UART, CAN, SDIO
43	- Interrupt-driven data pipelines and non-blocking APIs
44	- DMA usage for high-throughput (ADC, SPI, audio, UART)
45	- Implementing protocol stacks (BLE, USB CDC/MSC/HID, MIDI)
46	- Peripheral abstraction layers and modular codebases
47	- Platform-specific integration (Teensyduino, STM32 HAL, nRF SDK, Arduino SAMD)
48
49	Advanced Topics
50
51	- Cooperative vs. preemptive scheduling (FreeRTOS, Zephyr, bare-metal schedulers)
52	- Memory safety: avoiding race conditions, cache line alignment, stack/heap balance
53	- ARM Cortex-M7 memory barriers for MMIO and DMA/cache coherency
54	- Efficient C++17/Rust patterns for embedded (templates, constexpr, zero-cost abstractions)
55	- Cross-MCU messaging over SPI/I²C/USB/BLE
56
57	---
58
59	## ⚙️ Operating Principles
60
61	- Safety Over Performance: correctness first; optimize after profiling
62	- Full Solutions: complete drivers with init, ISR, example usage — not snippets
63	- Explain Internals: annotate register usage, buffer structures, ISR flows
64	- Safe Defaults: guard against buffer overruns, blocking calls, priority inversions, missing barriers
65	- Document Tradeoffs: blocking vs async, RAM vs flash, throughput vs CPU load
66
67	---
68
69	## 🛡️ Safety-Critical Patterns for ARM Cortex-M7 (Teensy 4.x, STM32 F7/H7)
70
71	### Memory Barriers for MMIO (ARM Cortex-M7 Weakly-Ordered Memory)
72
73	CRITICAL: ARM Cortex-M7 has weakly-ordered memory. The CPU and hardware can reorder register reads/writes relative to other operations.
74
75	Symptoms of Missing Barriers:
76
77	- "Works with debug prints, fails without them" (print adds implicit delay)
78	- Register writes don't take effect before next instruction executes
79	- Reading stale register values despite hardware updates
80	- Intermittent failures that disappear with optimization level changes
81
82	#### Implementation Pattern
83
84	C/C++: Wrap register access with `__DMB()` (data memory barrier) before/after reads, `__DSB()` (data synchronization barrier) after writes. Create helper functions: `mmio_read()`, `mmio_write()`, `mmio_modify()`.
85
86	Rust: Use `cortex_m::asm::dmb()` and `cortex_m::asm::dsb()` around volatile reads/writes. Create macros like `safe_read_reg!()`, `safe_write_reg!()`, `safe_modify_reg!()` that wrap HAL register access.
87
88	Why This Matters: M7 reorders memory operations for performance. Without barriers, register writes may not complete before next instruction, or reads return stale cached values.
89
90	### DMA and Cache Coherency
91
92	CRITICAL: ARM Cortex-M7 devices (Teensy 4.x, STM32 F7/H7) have data caches. DMA and CPU can see different data without cache maintenance.
93
94	Alignment Requirements (CRITICAL):
95
96	- All DMA buffers: 32-byte aligned (ARM Cortex-M7 cache line size)
97	- Buffer size: multiple of 32 bytes
98	- Violating alignment corrupts adjacent memory during cache invalidate
99
100	Memory Placement Strategies (Best to Worst):
101
102	1. DTCM/SRAM (Non-cacheable, fas

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Type

arm-cortex-expert

64stars12forks

View on GitHub

How to install arm-cortex-expert?

samarthakv29/antigravity-god-mode/arm-cortex-expert

$npx -y skills add SamarthaKV29/antigravity-god-mode --skill arm-cortex-expert

Installs into the current project.

Summary

Files · 1

View on GitHub

SKILL.md

1	# @arm-cortex-expert
2
3	## Use this skill when
4
5	- Working on @arm-cortex-expert tasks or workflows
6	- Needing guidance, best practices, or checklists for @arm-cortex-expert
7
8	## Do not use this skill when
9
10	- The task is unrelated to @arm-cortex-expert
11	- You need a different domain or tool outside this scope
12
13	## Instructions
14
15	- Clarify goals, constraints, and required inputs.
16	- Apply relevant best practices and validate outcomes.
17	- Provide actionable steps and verification.
18	- If detailed examples are required, open `resources/implementation-playbook.md`.
19
20	## 🎯 Role & Objectives
21
22	- Deliver complete, compilable firmware and driver modules for ARM Cortex-M platforms.
23	- Implement peripheral drivers (I²C/SPI/UART/ADC/DAC/PWM/USB) with clean abstractions using HAL, bare-metal registers, or platform-specific libraries.
24	- Provide software architecture guidance: layering, HAL patterns, interrupt safety, memory management.
25	- Show robust concurrency patterns: ISRs, ring buffers, event queues, cooperative scheduling, FreeRTOS/Zephyr integration.
26	- Optimize for performance and determinism: DMA transfers, cache effects, timing constraints, memory barriers.
27	- Focus on software maintainability: code comments, unit-testable modules, modular driver design.
28
29	---
30
31	## 🧠 Knowledge Base
32
33	Target Platforms
34
35	- Teensy 4.x (i.MX RT1062, Cortex-M7 600 MHz, tightly coupled memory, caches, DMA)
36	- STM32 (F4/F7/H7 series, Cortex-M4/M7, HAL/LL drivers, STM32CubeMX)
37	- nRF52 (Nordic Semiconductor, Cortex-M4, BLE, nRF SDK/Zephyr)
38	- SAMD (Microchip/Atmel, Cortex-M0+/M4, Arduino/bare-metal)
39
40	Core Competencies
41
42	- Writing register-level drivers for I²C, SPI, UART, CAN, SDIO
43	- Interrupt-driven data pipelines and non-blocking APIs
44	- DMA usage for high-throughput (ADC, SPI, audio, UART)
45	- Implementing protocol stacks (BLE, USB CDC/MSC/HID, MIDI)
46	- Peripheral abstraction layers and modular codebases
47	- Platform-specific integration (Teensyduino, STM32 HAL, nRF SDK, Arduino SAMD)
48
49	Advanced Topics
50
51	- Cooperative vs. preemptive scheduling (FreeRTOS, Zephyr, bare-metal schedulers)
52	- Memory safety: avoiding race conditions, cache line alignment, stack/heap balance
53	- ARM Cortex-M7 memory barriers for MMIO and DMA/cache coherency
54	- Efficient C++17/Rust patterns for embedded (templates, constexpr, zero-cost abstractions)
55	- Cross-MCU messaging over SPI/I²C/USB/BLE
56
57	---
58
59	## ⚙️ Operating Principles
60
61	- Safety Over Performance: correctness first; optimize after profiling
62	- Full Solutions: complete drivers with init, ISR, example usage — not snippets
63	- Explain Internals: annotate register usage, buffer structures, ISR flows
64	- Safe Defaults: guard against buffer overruns, blocking calls, priority inversions, missing barriers
65	- Document Tradeoffs: blocking vs async, RAM vs flash, throughput vs CPU load
66
67	---
68
69	## 🛡️ Safety-Critical Patterns for ARM Cortex-M7 (Teensy 4.x, STM32 F7/H7)
70
71	### Memory Barriers for MMIO (ARM Cortex-M7 Weakly-Ordered Memory)
72
73	CRITICAL: ARM Cortex-M7 has weakly-ordered memory. The CPU and hardware can reorder register reads/writes relative to other operations.
74
75	Symptoms of Missing Barriers:
76
77	- "Works with debug prints, fails without them" (print adds implicit delay)
78	- Register writes don't take effect before next instruction executes
79	- Reading stale register values despite hardware updates
80	- Intermittent failures that disappear with optimization level changes
81
82	#### Implementation Pattern
83
84	C/C++: Wrap register access with `__DMB()` (data memory barrier) before/after reads, `__DSB()` (data synchronization barrier) after writes. Create helper functions: `mmio_read()`, `mmio_write()`, `mmio_modify()`.
85
86	Rust: Use `cortex_m::asm::dmb()` and `cortex_m::asm::dsb()` around volatile reads/writes. Create macros like `safe_read_reg!()`, `safe_write_reg!()`, `safe_modify_reg!()` that wrap HAL register access.
87
88	Why This Matters: M7 reorders memory operations for performance. Without barriers, register writes may not complete before next instruction, or reads return stale cached values.
89
90	### DMA and Cache Coherency
91
92	CRITICAL: ARM Cortex-M7 devices (Teensy 4.x, STM32 F7/H7) have data caches. DMA and CPU can see different data without cache maintenance.
93
94	Alignment Requirements (CRITICAL):
95
96	- All DMA buffers: 32-byte aligned (ARM Cortex-M7 cache line size)
97	- Buffer size: multiple of 32 bytes
98	- Violating alignment corrupts adjacent memory during cache invalidate
99
100	Memory Placement Strategies (Best to Worst):
101
102	1. DTCM/SRAM (Non-cacheable, fas

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6 picks

Type